Content addressable memories (“CAMs”) are commonly used in cache and other address translation systems of high speed computing systems. Ternary content addressable memories (“TCAMs”) are ternary state CAM cells and are commonly used for parallel search in high performance computing systems. The unit of data stored in a TCAM bitcell is ternary, i.e., having three possible states: logic one, logic zero, and don't care state (referred to as an “X” state). To store these three states, TCAM bitcells include a pair of memory elements.
CAMs permit its memory cells to be referenced by their contents. Thus, CAMs have found use in lookup table implementations such as cache memory subsystems and are now rapidly finding use in networking system applications such as network address translation, and other applications such as pattern recognition and data compression. CAMs' most valuable feature is its ability to perform a fast search operation in which search data is compared with stored data. Typically, a searched data word is loaded onto search lines and compared with stored data words in the CAMs. The stored data words are compared bit-by-bit with the searched data word. During a search-and-compare operation, the CAMs perform a parallel search and generates match or mismatch signal associated with each stored data word, indicating whether the search word matches any of the stored data words.
FIG. 1 illustrates a prior art block diagram for TCAM unit cells connected to a match line sense amplifier. TCAM bitcells 10 that form a data entry can be connected along the same row and connected to a match line ML, word lines WLY and WLX, and search lines ST and SC. A match line sense amplifier 20 is connected to an end of the match line. Each of the TCAM bitcells 10 comprise two static random-access memory (“SRAM”) cells (or dynamic random access memory (“DRAM”) cells, depending on the implementation) and a compare circuit 12 (e.g., an XOR circuit) to compare the data within the respective TCAM bitcell with bits of the searched data word.
An indication of a match or mismatch is indicated on the match line. The compare circuits 12 of the TCAM cells 10 of a stored data word can have their respective outputs logically dotted together in a dot-XOR structure via the match line. If any of the compare circuits 12 are on (i.e., driving the match line to a low state to indicate a mismatch), a mismatch can be identified for that respective stored data word. If the match line goes to a high state, then the stored data word can be identified as a match and the location of that data entry is outputted.
FIG. 2 illustrates a prior art block diagram for compare circuits of TCAM bitcells connected to a match line sense amplifier. As indicated above, the compare circuits 12 of the TCAM data entry are connected together via the match line. Due to the large number of compare circuits 12, the match line can be highly capacitive. The match line is further coupled to a match line sense amplifier 20 at one end of the match line to charge the match line and to detect a voltage on the match line. Due to their inherent parallel structure and charging required for operation, the match line can consume large amounts of power. For this reason, TCAMs require relatively high power and large current pulses to operate the compare function circuitry (e.g., match and search line pulsing) and for match line sensing. In order to produce fast compare circuits, large amounts of power are consumed to quickly recharge the match line to its high state in preparation for another data match comparison. Because the match line is highly capacitive and the match line sense amplifier is high powered to quickly charge the match line, a phenomena known as snap back occurs.
FIG. 3A illustrates a prior art block diagram of an equivalent circuit for a match line sense amplifier 20. The match line sense amplifier 20 is coupled to match line 23 and includes a match line charger 21 controlled by signal CM_B, and a sense inverter 22. The equivalent circuit of match line 23 includes a plurality of nFET stacks 24 and a resistor between the nFET stacks 24 which represent an equivalent resistance of a section of the metal match line 23. Match line 23 is a single line with a match line far end, ML_FAR, and a match line near end, ML_NEAR. The ML_NEAR end is coupled to the input of match line sense amplifier 20. For ease of understanding and not to obscure the invention with detailed signals, match line charger 21 charges the match line 23 to a high state when signal charge match, CM_B goes to a low state, the signal CM_B denotes an active low. Stated differently, as signal CM_B become active, the match line 23 is charged until a voltage at the input of sense inverter 22 of the sense amplifier 20 becomes a high state and turns off the signal CM_B. The match line has a given length and there is a metal resistance associated with the length. As the match line charger 21 quickly charges the match line 23, voltage throughout the match line 23 cannot change instantaneously and there is noticeable delay before the voltage reaches a steady state throughout the length of the match line 23. For example, a voltage measurement at match line near end, ML_NEAR is different from a voltage measurement at match line far end, ML_FAR because metal resistance and capacitance of the match line 23 introduces an RC time constant delay as the match line is robustly charged.
FIG. 3B illustrates a voltage vs time graph showing a snap back phenomena of a prior art match line. Graph 32 represents the output of sense inverter 22. As the voltage on the match line is quickly charged at the match line near end, voltage at ML_NEAR of the match line as shown by graph 34 increases in excess of the match line trip voltage at which point the match line charger 21 is turned off. A snap back phenomenon occurs as the voltage shown by graph 34 falls back to the match line far end, ML_FAR of the match line as shown by dotted graph 36. The voltage at the far end of the match line ML_FAR lags behind the voltage at the near end due to capacitance and resistance of the match line. Given enough time, the voltage at the match line near end, ML_NEAR and the match line far end, ML_FAR of the match line will eventually merge. However, since the sense inverter 22 senses voltage at the match line near end, ML_NEAR, and the overshoot is at the match line near end, ML_NEAR, the overshoot can reach the trip point of the sense inverter 22 thereby stopping the charge to the match line. Problem arises when the difference from the snap back voltage causes the sense inverter 22 to trip prematurely. Referring to graph 34, the trip point of the sense inverter 22 is set at approximately 400 millivolts. Because of the snap back phenomenon, the sense inverter 22 can be tripped when the voltage from graph 34 reaches the highest point. As the match line charger 21 is turned off, the voltage at the ML_NEAR and the voltage at the ML_FAR charge equalize, which cause the voltage at the ML_NEAR to snap back. The snap back phenomenon can cause the match line sense amplifier 20 to begin charging again. The snap back phenomenon causes havoc to match line sense amplifiers for single ended line sensing. As devices become smaller and voltage margins become tighter, the snap back phenomenon becomes even more of a problem for circuit designers.
For the foregoing reasons, there is a need for new methods and apparatuses for a sense amplifier the overcome the problem associated with quickly charging a single match line for single ended line sensing.